Reducing warpage for fan-out wafer level packaging

ABSTRACT

Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface, a plurality of side surfaces, and a bond pad defined on the top surface. A layer of encapsulant substantially surrounds the side surfaces of the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit. A bump is spaced apart from the integrated circuit, and a redistribution layer electrically couples the bond pad of the integrated circuit to the bump.

BACKGROUND

1. Technical Field

This description generally relates to the field of chip packaging, andmore particularly to fan-out wafer level packaging.

2. Description of the Related Art

Redistributing the bond pads of integrated circuits (“ICs”) in chippackages is becoming increasingly common. In general, the redistributionprocess converts peripheral wire bond pads on an IC to an area array ofsolder bumps via a redistribution layer. The resulting fan-out waferlevel packaging may have a larger solder bump bonding area and may bemore easily integrated into electronic devices and larger chip packages.

Referring to FIG. 1, conventional fan-out wafer level packaging isillustrated. Conventionally, a backside of an IC 2 is first encapsulatedin a molding compound 1. A plurality of dielectric layers 4 andredistribution layers 3 are then deposited on a front side of the IC 2to form electrical connections between wire bond pads 7 on the IC 2 andredistributed solder bump bond pads 5. Finally, solder bumps 6 areformed at the redistributed bond pad locations 5, and the fan-out waferlevel packaging is ready to be soldered to a printed circuit board.

FIG. 2 illustrates the encapsulation process as applied to a pluralityof ICs 2 arranged on a surface, such as a tape 8 on a carrier 9. Themold compound 1 is dispensed centrally on the tape 8 at a thicknesssufficient to completely cover all exposed surfaces of each IC 2. TheICs 2 are placed in a mold chase 10 that is configured to compress themolding compound 1 down and around all of the ICs 2. A large amount ofmolding compound 1 is required to ensure that all side surfaces and thebackside of each IC 2 is completely covered.

As shown in FIG. 3, prior to compressing the mold compound 1 down aroundthe ICs 2 a protective film 11 is arranged over the molding compound 1and across exterior edges 12, 13 of the mold chase. The protective film11 decreases the amount of compressive force applied to the ICs 2.Subsequently, the molding compound 1 is compressed down and spreadsaround each of the ICs 2.

Unfortunately, after employing such packaging methods, the backside ofthe IC 2 is typically covered by a relatively thick layer of the moldingcompound 1, as illustrated in FIG. 1. As a result, this can result inincreased warping of the packaging due to coefficient of thermalexpansion mismatch, and the thickness of the packaging.

There remains a need in the art, therefore, for an improved method ofmanufacturing fan-out wafer level packaging.

BRIEF SUMMARY

A method of packing a die in which an encapsulation layer is formedaround the four sides of an integrated circuit and is not formed on thefront side or the back side, thus providing a package die in which aninactive surface of the integrated circuit is not covered by theencapsulation layer. Integrated circuits are often packaged inencapsulation layers, such as molding compounds, to protect the circuitelements. The front side has bonding pads on the integrated circuitscoupled to soldering bumps for future connection to a larger circuit,such as a motherboard of a computer, whereas the backside is exposed orhas a thin layer of epoxy covering it.

According to one embodiment of the present disclosure, an integratedcircuit is first placed on an adhesive tape. An active surface of theintegrated surface adheres to the tape so that the inactive surface isexposed, extending away from the tape. The tape is not rigid, but ratherflexible and may act as a cushion for the integrated circuit. The tapeis attached to a rigid carrier that supports the tape having theintegrated circuit for transportation between processes. The tape andthe carrier are attached in a manner that allows the two pieces to moveas one.

A molding chamber is provided that is sized and shaped to receive theintegrated circuit attached to the tape and carrier. A molding compoundis melted in the molding chamber. Subsequently, the carrier and tapecombination is turned over so the inactive surface of the integratedcircuit contacts the molding compound in the molding chamber first. Thecarrier and tape are then compressed to press the integrated circuitinto the molding compound.

A protective layer lines the interior surfaces of the molding chamber.The protective layer may be plastic or any material that is flexible andnot rigid. The integrated circuit is compressed into the molding chamberuntil the inactive surface contacts the protective layer. Both the tapeand the protective layer prevent damage to the integrated circuit byabsorbing the compressive stress.

A method of manufacturing fan-out wafer level packaging is disclosed.The method comprises: positioning an integrated circuit on a firstsurface; forming a layer of encapsulant on the first surfacesubstantially surrounding the integrated circuit, the layer ofencapsulant having a height substantially equal to a height of theintegrated circuit; forming a redistribution layer configured toelectrically couple a bond pad of the integrated circuit to aredistributed bond pad; and forming a bump at the redistributed bondpad.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

In the drawings, identical reference numbers identify similar elementsor acts. The sizes and relative positions of elements in the drawingsare not necessarily drawn to scale. For example, the shapes of variouselements and angles are not drawn to scale, and some of these elementsare enlarged and positioned to improve drawing legibility. Further, theparticular shapes of the elements as drawn, are not intended to conveyany information regarding the actual shape of the particular elements,and have been solely selected for ease of recognition in the drawings.

FIG. 1 is a cross-sectional, side, schematic view of prior art fan-outwafer level packaging.

FIGS. 2 and 3 are cross-sectional side views of a prior art process offorming the wafer level packaging of FIG. 1.

FIG. 4 is a cross-sectional, side, schematic view of fan-out wafer levelpackaging, according to one embodiment.

FIGS. 5 and 6 illustrate a first plurality of processing acts that maybe used in manufacturing the fan-out wafer level packaging of FIG. 4,according to one embodiment.

FIGS. 7A-7C illustrate an encapsulation process in accordance with oneembodiment.

FIGS. 8-13 illustrate a second plurality of processing acts that may beused in manufacturing the fan-out wafer level packaging of FIG. 4,according to one embodiment.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

In the following description, certain specific details are set forth inorder to provide a thorough understanding of various disclosedembodiments. However, one skilled in the relevant art will recognizethat embodiments may be practiced without one or more of these specificdetails, or with other methods, components, materials, etc. In otherinstances, well-known structures and methods associated with integratedcircuits and semiconductor manufacturing/packaging processes have notbeen shown or described in detail to avoid unnecessarily obscuringdescriptions of the embodiments.

Unless the context requires otherwise, throughout the specification andclaims which follow, the word “comprise” and variations thereof, suchas, “comprises” and “comprising” are to be construed in an open,inclusive sense, that is, as “including, but not limited to.”

Reference throughout this specification to “one embodiment” or “anembodiment” means that a particular feature, structure or characteristicdescribed in connection with the embodiment is included in at least oneembodiment. Thus, the appearances of the phrases “in one embodiment” or“in an embodiment” in various places throughout this specification arenot necessarily all referring to the same embodiment. Furthermore, theparticular features, structures, or characteristics may be combined inany suitable manner in one or more embodiments.

As used in this specification and the appended claims, the singularforms “a,” “an,” and “the” include plural referents unless the contextclearly dictates otherwise. It should also be noted that the term “or”is generally employed in its sense including “and/or” unless the contextclearly dictates otherwise.

The headings and Abstract of the Disclosure provided herein are forconvenience only and do not interpret the scope or meaning of theembodiments.

Description of an Exemplary Fan-Out Wafer Level Packaging

FIG. 4 shows fan-out wafer level packaging 100, according to oneillustrated embodiment. The fan-out wafer level packaging 100 may beconfigured to at least partially protect an integrated circuit 102 fromthe external environment. In other embodiments, the fan-out wafer levelpackaging 100 is configured to include a plurality of bumps 104electrically coupled to the integrated circuit 102, and the fan-outwafer level packaging 100 may thus enable electrical connections to beformed between the integrated circuit 102 and external circuitry. Inother embodiments, other electrically conductive structures may beformed along an external surface of the fan-out wafer level packaging100 in order to enable such electrical connections with the integratedcircuit 102.

The integrated circuit 102 includes a variety of electronic circuitry.For example, the integrated circuit 102 may comprise a controller for anelectronic computing device, or a computer-readable memory. In differentembodiments, the integrated circuit 102 may be formed using any of avariety of semiconductor fabrication processes. In one embodiment, theintegrated circuit 102 is defined by layers of semi-conducting,dielectric and conducting materials deposited onto a semiconductorsubstrate in accordance with pre-defined patterns.

Recent integrated circuits can use different materials for theintegrated circuit construction than previously used. For many years,standard silicon dioxide, silicon nitride, and polysilicon layers wereused to construct various interconnection layers between the substrateand the operational transistors that formed the integrated circuit.Initial circuits made some years ago had one or two layers ofpolysilicon on top of which may be one or two layers of metal. Recentadvances in semiconductor technology have drastically increased thecomplexity of integrated circuits. Many circuits may have between twoand five layers of polysilicon and between seven and twelve layers ofmetal above the polysilicon layers. Further, the size of the minimumgate width of transistors has shrunk dramatically with transistors inthe range of 65 nm, 45 nm, and 32 nm becoming common. Future transistorsizes may approach 20 or 18 nm for the gate length.

Another improvement further increasing the complexity is the use of manydifferent types of dielectric layers between the substrate and the firstmetal layer and between various metal layers. For example, an uppermostpolysilicon layer may be positioned over a plurality of insulatinglayers, which can include various nitride and oxide layers as well as aplurality of additionally polysilicon layers separated from each otherby various sublayers of silicon nitride, silicon dioxide, and othertypes of insulators. Additionally, metal layers may be formed with apremetal dielectric layer composed of a plurality of sublayers. In smallgeometry silicon chips, such as 90 nm and smaller, the premetaldielectrics are usually made of a low-k material. This low-k materialmay be an aerogel, a nanoporous dielectric, or other extremely low-kdielectric material. The low-k dielectric layers may be composed of aplurality of low-k dielectric layers and followed by yet another metallayer. This continues for many layers and sublayers.

In the prior art, dielectric layers between the various metal layers maybe composed of one or perhaps two glass layers, such as a spin-on glass,a silicon dioxide glass, or other strong layers which had high adhesiveproperties, and bonded strongly to each other. On the other hand, themore modern chips, use dielectric materials which have numerous smallpockets of air distributed throughout in order to reduce the dielectricconstant. Such low-k dielectric materials are not as structurally strongas a more solid glass, such as a spin-on glass or a solid silicondioxide glass. In addition, these layers often contain chemicalcompositions which do not stick as tightly to each other as the priorart glasses. Such dielectric compounds may contain various combinationsof carbon, fluoride, hydrogen, and other elements to increase theporosity and reduce the dielectric constant. These low-k dielectricsprovide enhanced electrical performance, but the structural integrity issubstantially less than was provided in prior art semiconductor devices.In addition, the adhesive bonding strength between the various layers isreduced.

Repeated cycles of heating and cooling are problematic to the structuralintegrity of integrated circuits with many low-k dielectric layers. Whenthe integrated circuit 102 is heated or cooled, it expands or shrinksaccording to a coefficient of thermal expansion (CTE) particular to thematerial of the integrated circuit 102. Each dielectric layer may have aslightly different CTE coefficient of expansion during heating. Amaterial with a high CTE will expand or shrink more than a material witha lower CTE under a given increase or decrease in temperature. When thepackage is heated or cooled, the molding compound, the integratedcircuit 102, the substrate, and the sublayers expand or contractdifferently from each other. This disparity in expansion causes theintegrated circuit 102 to experience compressive, expansive, and tensileforces. The stress is felt more intensely at the edges and corners ofthe integrated circuit 102. The repeated cycles of expansion andcontraction may eventually cause layers in the integrated circuit towarp and separate. If a crack propagates from the inactive surface tothe integrated circuitry, the crack can be fatal to the functionality ofthe integrated circuit.

The repeated stresses may also cause delamination of the layers in theintegrated circuit 102. Delamination is the separation or unbending ofany of the layers, sublayers, or components of the integrated circuit102. For example, under stress, the adhesion between the various layersin integrated circuit 102 may fail. Delamination between any of thecomponents can damage functionality of the integrated circuit.

The stresses also cause warping of the integrated circuit 102. Thestress of the expansion and contraction of the components of the packagecan cause curvature of the integrated circuit 102. This curvature, whichis focused at the edges and corners of the integrated circuit 102, canresult in poor solder joint formation in certain kinds of packages.Furthermore, the curvature can result in a loss of functionality of theintegrated circuit 102.

In applications where a small dielectric constant is needed (low kapplications), a porous silicon is often used as a dielectric betweencircuit components and layers of the integrated circuit. The poroussilicon is particularly prone to fracturing under stress. Any warping ofthe integrated circuit 102 can cause fracturing of the porous silicon.Compressive forces of contraction and expansion may also cause theporous silicon to fracture. This fracturing can damage functionality ofthe integrated circuit.

The effects of thermo-mechanical stress are greater with largerintegrated circuit 102 size. With system on chip (SOC) technology,integrated circuit 102 sizes increase due to the number of systems beingintegrated into one integrated circuit. Stress at the corners and edgesof a larger integrated circuit 102 cause greater torque on theintegrated circuit 102 and can more easily cause cracking, warping, ordelamination of the integrated circuit 102. The present invention isdesigned to prevent these problems in the large integrated circuit 102 shaving low-k dielectrics.

As illustrated, the integrated circuit 102 includes a front or topsurface 106 and a back side or bottom surface 108. Of course, the terms,top and bottom, should not be understood to imply any absolutepositioning of the integrated circuit 102, rather, front or top refersto the surface having the circuits therein and the back side or bottomis the other side of pure silicon. The back side 108 is exposed in thefinal package in one embodiment; in other embodiments it may have a thinlayer of silicon carbide, resin or an epoxy or other passivation layer.Having the back side 108 exposed or having a thin covering of resin,epoxy or the like ensures reduced stress due to a thermal mismatch ofthe package holding the die. The packing resin material 112 will have adifferent Coefficient of Thermal Expansion, CTE, from the die 102, byhaving a small amount of resin on the sides and either a thin or nolayer on the back side, stress caused by differences in CTE of thedifferent materials is kept low.

The integrated circuit 102 may further include a plurality of sidesurfaces 110. Although not visible in FIG. 2, the integrated circuit 102may further include one or more bond pads defined on the top surface106. The number of bond pads may vary greatly depending upon theparticular application for the integrated circuit 102. For example,controller circuitry may require more bond pads defining input/outputsthan memory circuitry. The bond pads may comprise any type of conductingmaterial, such as copper, silver, or gold.

The integrated circuit 102 may have any of a variety of shapes andsizes. In one embodiment, the integrated circuit 102 has a generallyrectilinear top surface 106. For example, the top surface 106 may have agenerally square shape, and thus the integrated circuit 102 may includefour side surfaces 110. In other embodiments, more irregular shapes maydefine the integrated circuit 102.

The fan-out wafer level packaging 100 may further comprise a layer ofencapsulant 112 substantially surrounding the side surfaces 110 of theintegrated circuit 102. The layer of encapsulant 112 may comprise any ofa variety of encapsulants, such as a molding compound. In oneembodiment, the encapsulant comprises a dielectric material that servesto electrically insulate as well as at least partially protect theintegrated circuit 102 from the external environment.

The layer of encapsulant 112, like the integrated circuit 102, may haveany of a variety of shapes and sizes. As illustrated, the layer ofencapsulant 112 has a height substantially equal to a height of theintegrated circuit 102. In one embodiment, the layer of encapsulant 112has a height that is less than 20% greater than a height of theintegrated circuit 102. In other embodiments, the height of the layer ofencapsulant 112 is less than 10% greater than the height of theintegrated circuit 102. In still other embodiments, the height of thelayer of encapsulant 112 is equal to the height of integrated circuit102. In one embodiment, by making the height of the layer of encapsulant112 substantially equal to the height of the integrated circuit 102, thepotential for warpage can be substantially reduced. The layer ofencapsulant 112 may further have a generally rectilinear outerperimeter, such that the shape of the layer of encapsulant 112 and theshape of the integrated circuit 102 are geometrically similar.

The fan-out wafer level packaging 100 may further include one or morebumps 104 positioned proximate a top surface 114 of the fan-out waferlevel packaging 100. Each of these bumps 104 is spaced apart from theintegrated circuit 102, but may be electrically coupled thereto. Thebumps 104 may comprise any of a variety of solder bumps formed fromdifferent materials. In one embodiment, the bumps 104 comprise lead-freesolder bumps, while, in other embodiments, the bumps 104 include lead aswell as other conductive materials, such as tin. Although two bumps 104are visible in the cross-section of FIG. 2, more bumps 104 areincorporated into the fan-out wafer level packaging 100 in differentembodiments. For example, in some embodiments, at least one bump 104 maycorrespond to each bond pad defined on the top surface 106 of theintegrated circuit 102.

The bumps 104 may also have any of a variety of sizes. In oneembodiment, the bumps 104 have diameters of between 10 and 200 μm,depending upon their composition, as well as the processes used to formthem.

The fan-out wafer level packaging 100 may further include aredistribution layer 116, also called a wiring layer or solder ball tobond pad coupling layers, configured to electrically couple a bond padof the integrated circuit 102 to a corresponding bump 104. Theredistribution layer 116 may comprise any of a variety of electricallyconductive materials defining at least part of an electrical pathbetween particular bond pads of the integrated circuit 102 andcorresponding bumps 104. For example, the redistribution layer 116 maycomprise copper or gold in some embodiments.

In one embodiment, as illustrated in FIG. 4, the redistribution layer116 itself may include redistributed bond pads (located directlyunderneath corresponding bumps 104), and the bumps 104 may be in directcontact with the redistribution layer 116. However, in otherembodiments, redistributed bond pads may be formed atop theredistribution layer 116 (as discussed in greater detail below), and thebumps 104 may be coupled thereto.

The redistribution layer 116 may have any of a variety of thicknesses.In one embodiment, the redistribution layer 116 may be between 1 and 10μm thick. Such a substantial thickness may facilitate the use of theredistribution layer 116 itself as a redistributed bond pad withlead-free bumps. In other embodiments, the redistribution layer 116 maybe at least 1 μm thick. In such embodiments, it may be desirable to usethe redistribution layer 116 with a separate redistributed bond pad toform the final interface with a corresponding bump 104.

The fan-out wafer level packaging 100 may further include dielectriclayers 118, 120. Such dielectric layers 118, 120 may add structuralintegrity to the fan-out wafer level packaging 100, while keepingconductive elements of the fan-out wafer level packaging 100electrically insulated from one another. In one embodiment, a firstdielectric layer 118 extends at least partially over the top surface 106of the integrated circuit 102. The first dielectric layer 118 may defineat least one bond pad via, through which the redistribution layer 116may contact a corresponding bond pad of the integrated circuit 102. Twosuch bond pad vias are illustrated in the cross-sectional view of FIG.4. Of course, in other embodiments, more or fewer bond pad vias may bedefined.

In one embodiment, a second dielectric layer 120 extends at leastpartially over the redistribution layer 116. The second dielectric layer120 may define at least one redistribution via therethrough that extendsto the redistribution layer 116. Two such redistribution vias areillustrated in the cross-sectional view of FIG. 2. Of course, in otherembodiments, more or fewer redistribution vias may be defined. In oneembodiment, each redistribution via through the second dielectric layer120 may correspond to exactly one bond pad via through the firstdielectric layer 118.

In one embodiment, the first dielectric layer 118 and the seconddielectric layer 120 comprise the same dielectric material. For example,a photosensitive polymer, such as polyimide, polybenzoxazole or solderresist, may be used to define both the first dielectric layer 118 andthe second dielectric layer 120. In other embodiments, differentmaterials may be used to define the two dielectric layers 118, 120.

The first dielectric layer 118 may have any of a variety of thicknesses.In one embodiment, the first dielectric layer 118 may be betweenapproximately 5 and 10 μm thick, as measured from the top surface 106 ofthe integrated circuit 102 to the redistribution layer 116. The seconddielectric layer 120 may also be formed to define any of a variety ofthicknesses. In one embodiment, a thickness of the second dielectriclayer 120 may be greater than 2 μm added to a thickness of theredistribution layer 116.

Description of an Exemplary Method for Manufacturing Fan-Out Wafer LevelPackaging

FIGS. 5-13 illustrate different processing acts that may be used in amethod of manufacturing fan-out wafer level packaging, according to oneembodiment. This method will be discussed in the context of the fan-outwafer level packaging 100 of FIG. 4. However, it may be understood thatthe acts disclosed herein may also be executed to manufacture a varietyof differently configured fan-out wafer level packaging, in accordancewith the described method.

As described herein, all of the acts comprising the method may beorchestrated by a manufacturing processor or controller based at leastin part on execution of computer-readable instructions stored in memory.In other embodiments, a hardware implementation of all or some of theacts of the manufacturing method may be used.

First, a plurality of integrated circuits 102 may be formed by any of avariety of manufacturing processes. In one embodiment, as illustrated inFIG. 5, a wafer 300 including a plurality of integrated circuits 102 isprovided. The wafer 300 may be processed in accordance with a variety ofsemiconductor processing techniques to form the integrated circuits 102,and, in one embodiment, each of the integrated circuits 102 definedwithin the wafer 300 may be similarly configured. The wafer 300 may thenbe divided (e.g. by laser-cutting or die sawing) to define theindividual integrated circuits 102. Although illustrated as round, thewafer 300 may also comprise a square panel ranging in size from 8″×8″ upto 12″×12″.

Once separated, the integrated circuits 102 may be positioned on asurface 302 of a backing 304. The backing 304 may comprise any of avariety of surfaces, and, in one embodiment, the backing 304 maycomprise an adhesive surface of a piece of tape. In one embodiment, onlya single integrated circuit 102 may be positioned on the piece of tape;however, in other embodiments, as illustrated, a plurality of integratedcircuits 102 may be positioned in an array thereon.

The integrated circuits 102 may be placed atop the surface 302 in avariety of ways. For example, in one embodiment, a robotic end effectormay be used to properly position the integrated circuits 102. In anotherembodiment, a human operator places the integrated circuit 102 manuallyor by a user-controlled machine. The integrated circuits 102 may bepositioned with the top surface 106 of the integrated circuits 102facing the surface 302. The top surface 106 may correspond to the areaof the integrated circuit 102 that contains active regions as opposed toa silicon substrate. The integrated circuits 102 are spaced on thesurface 302 by a predetermined distance to ensure sufficient space forsingulating the ICs later in the process.

A layer of encapsulant 112 may then be formed on the first surface 302substantially surrounding the integrated circuits 102, as shown in FIG.6. The layer of encapsulant 112 has a height substantially equal to aheight of the integrated circuits 102. The layer of encapsulant 112 maybe formed by any of a variety of manufacturing processes.

FIGS. 7A-7C illustrate a manufacturing process for forming theencapsulation layer 112 of a height substantially similar to the heightof the IC 102. A predetermined amount of encapsulant 112 is placed on aprotective layer 208 in a mold chase 200. The protective layer 208 maybe formed of plastic or other material that is not rigid. The protectivelayer 208 is configured to depress or otherwise cushion the inactivesurface, i.e. the bottom surface 108, of the integrated circuit 102 whenthe inactive surface is compressed onto the protective layer 208, asdescribed below.

The encapsulant 112 may be a molding compound or a molding resin. Theencapsulant 112 may be in a liquid or a powder form. The mold chase 200may be formed of metal and is configured to heat the powder to a liquidform. If the encapsulant is initially liquid, the mold chase 200 isconfigured to maintain the liquid at a specific temperature inpreparation for application to the ICs 102. For example, the liquidencapsulant 112 may be kept at a temperature of 120 to 150 degreesCelsius. Additionally, the encapsulant may be used that is liquid atlower temperature and subsequently form crosslinks at highertemperatures. The crosslinks may cause the encapsulant to withstand moreheat after initial solidification so that the encapsulant does notre-melt if the IC 102 operates at a temperature higher than 120 degreesCelsius.

FIG. 7B illustrates the encapsulant in a molten form, evenly disbursedacross the entire mold chase 200. The protective layer 208, which may beplastic, completely covers all interior surfaces of the mold chase 200including top and side surfaces of walls 204 and 206. The protectivelayer 208 prevents the ICs 102 from contacting the hard metal surfacesof the mold chase 200. In one embodiment, the protective layer 208 is100 microns thick.

FIG. 7C illustrates the compressive molding of the encapsulant 112around the side surfaces 110 of the ICs 102. The backing 304 may beapplied to a carrier layer 306 before or after the ICs 102 are arrangedon the surface 302. As mentioned above, the backing 304 may be anadhesive tape that is elastic or otherwise flexible. The active surfaceof the integrated circuit, i.e., the top surface 106, is positioned onthe backing 304. The carrier layer 306 may be a plexiglass plate and mayprovide support for the backing. In addition, the carrier layer 306allows for transport of the ICs 102 to the mold chase 200. The carrierlayer 306 allows for the backing 304 and ICs 102 to be turned over sothat the bottom surfaces 108 of the ICs 102 enter the encapsulant 112 inthe mold chase 200 first.

A portion of the backing 304 and the carrier 306 extend past theexterior boundary 110 of the outermost IC 102 so that when turned overthe portion rests on the protective layer 208 over the top surface ofthe walls 204, 206. The walls 204, 206 have a height that corresponds toa height of the ICs 102 so that little or no encapsulant covers thebottom surface 108 of the IC 102. A compressive force is applied with acompressive member 210. The compressive member 210 is sized and shapedto correspond to the mold chase 200 and is configured to hold thecarrier 306 by vacuum suction. During compression, the mold chase 200 isunder pressure to remove air. The encapsulant 112 wicks around the sidesurfaces 110 of the ICs 102 as the compressive member presses down andthe air is removed. The encapsulant 112 covers all of the side surfaces110 of the ICs and is substantially the same height as the ICs. Theprotective layer 208 protects the IC 102 from any damage or scratchingthat may be caused by the compression. It also absorbs some of thecompression from the fluid resin 112, thus reducing the amount of stressplaced on the die 102 during the molding process.

As the compressive member 210 presses the carrier and the integratedcircuit into the mold chase 200, the integrated circuit is cushioned bythe backing 304 on the top surface 106 and by the protective layer 208on the bottom surface 108. The integrated circuit experiencesnon-compressive forces of the liquid encapsulant 112 only on the sides110. Liquid is non-compressable and by having the backing 304 and layer208 present, compressive forces on the sides of the die are reduced oreliminated. This significantly reduces the amount of compressive stressexperienced by the integrated circuit, which in turn significantlyreduces the problems of warpage during heating and cooling of thepackaged integrated circuit. Further as the hot resin 112 cools to forma solid, stress from the effects of difference in CTE are greatlyreduced.

In order to avoid excess encapsulant 112 in the mold chase and thereforeexcess encapsulant 112 over the backside 108 of the IC 102, the desiredweight of the encapsulant is calculated, then weighed as it is put inthe mold. Too much encapsulant 112 prevents the mold chase 200 andcompressive member 210 from pressing down the desired amount and causesthe final thickness of the encapsulant to be higher, so this is avoided.

Further processing steps may also be carried out. For example, theencapsulant may be heat-treated, cold-treated or otherwise processed inorder to change the chemical or physical characteristics of theencapsulant 112. In one embodiment, the encapsulant 112 is cured in somemanner. In other embodiments, other manufacturing processes for formingthe layer of encapsulant 112 may be used.

The piece of tape 304 may then be removed, as illustrated in FIG. 8, toleave what is effectively an array of integrated circuits 102 encased inthe layer of encapsulant 112. As described above, the top surface 106 ofthe integrated circuit 102 may have been facing towards the tape 304. Asoriented in FIG. 8, the top surface 106 of the integrated circuit 102 isfacing the top of the drawing. Upon removing the piece of tape 304, inone embodiment, the top surface 106 and the bottom surface 108 of theintegrated circuit 102 are both exposed, and the layer of encapsulant112 substantially covers four side surfaces 110 of the integratedcircuit 102.

In one embodiment, as illustrated in FIG. 9, a first dielectric layer118 may be formed extending at least partially over the top surface 106of the integrated circuit 102. The first dielectric layer 118 may beformed to include at least one bond pad via 122 through which at least aportion of a bond pad of the integrated circuit 102 is exposed. Thesebond pad vias 122 may enable subsequent electrical connections to beformed between the bond pads of the integrated circuit 102 and one ormore redistributed bond pads.

As described above, the first dielectric layer 118 may comprise any of avariety of dielectric materials. In one embodiment, the first dielectriclayer 118 comprises a photosensitive polymer, such as polyimide,polybenzoxazole, or solder resist.

The first dielectric layer 118 may also be deposited and then patternedto form the bond pad vias 122 by any of a variety of processes. If thefirst dielectric layer 118 comprises a photosensitive polymer, thephotosensitive polymer may first be coated over the layer of encapsulant112 and integrated circuit 102. After this coating, in some embodiments,the first dielectric layer 118 is planarized. Portions of the firstdielectric layer 118 may then be exposed to light (e.g., to ultravioletlight) to create a desired patterning in this layer 118. After the lightexposure, the exposed portions of the first dielectric layer 118 maythen be removed by application of a developer solvent if a positivephotosensitive polymer is used, or the unexposed portions may be removedif a negative photosensitive polymer is used. Of course, in otherembodiments, other patterning processes may be used. For example, aseparate photoresist layer may be deposited on top of the firstdielectric layer 118 in order to define and then transfer a desiredpattern to the first dielectric layer 118.

Additional chemical, physical or thermal processing may be carried outto cure or harden the first dielectric layer 118. For example, thepartially formed fan-out wafer level packaging 100 may be baked to curethe first dielectric layer 118.

As illustrated in FIG. 9, a redistribution layer 116 configured toelectrically couple the bond pad of the integrated circuit 102 to aredistributed bond pad may also be formed. The redistribution layer 116may comprise any of a variety of electrically conductive materials, asdiscussed above. As illustrated, the redistribution layer 116 may beformed over at least a portion of the first dielectric layer 118 and mayfill at least partially the bond pad via 122. Thus, the redistributionlayer 116 may create electrical connections between the bond pads of theintegrated circuit 102 and one or more redistributed bond pads throughthe bond pad vias 122.

In one embodiment, after the first dielectric layer 118 has been formed,a seed layer (not shown) may first be sputtered over the firstdielectric layer 118. The seed layer may comprise a metallic thin film,such as copper. This seed layer may thus extend over the entire exposedsurface of the partially formed fan-out wafer level packaging 100. Apatterned layer may then be formed over the seed layer usingphotolithography. Any of a variety of photolithographic techniques maybe used to form such a patterned layer over the seed layer. Thepatterned layer may comprise, for example, photoresist material. Thepatterned layer may leave portions of the seed layer exposed in apattern that will eventually define the pattern of the redistributionlayer 116. At least a portion of the seed layer exposed through thepatterned layer may then be plated to form the redistribution layer 116.For example, electrochemical plating or electroless plating may beperformed to create a copper redistribution layer 116. The patternedlayer may then be removed, and the remaining portions of the seed layerthat were not plated may also be removed. Any of a variety of chemicalor physical processes, such as wet etching, may be used to remove theselayers, leaving the patterned redistribution layer 116. Of course, inother embodiments, other techniques for forming a patternedredistribution layer 116 may be used.

As illustrated in FIG. 10, once the redistribution layer 116 has beenformed, a second dielectric layer 120 may be formed extending at leastpartially over the redistribution layer 116 and including at least oneredistribution via 124 through which at least a portion of theredistribution layer 116 is exposed. These redistribution vias 124 maydefine the locations for one or more redistributed bond pads. Asdescribed above, in one embodiment, the redistribution layer 116 mayitself define the redistributed bond pads. In other embodiments, aredistributed bond pad may be formed at least partially within acorresponding redistribution via 124, as described in greater detailbelow.

As described above, the second dielectric layer 120 may comprise any ofa variety of dielectric materials. In one embodiment, the seconddielectric layer 120 and the first dielectric layer 118 comprise thesame material. For example, the second dielectric layer 120 may comprisea photosensitive polymer, such as polyimide, polybenzoxazole or solderresist.

The second dielectric layer 120 may be deposited and then patterned toform the redistribution vias 124 in a variety of ways. If the seconddielectric layer 120 comprises a photosensitive polymer, thephotosensitive polymer may first be coated over the redistribution layer116 and exposed portions of the first dielectric layer 118. After thiscoating, in some embodiments, the second dielectric layer 120 isplanarized. Portions of the second dielectric layer 120 may then beexposed to light (e.g., to ultraviolet light) to create the desiredpatterning in this layer 120. After the light exposure, the exposedportions of the second dielectric layer 120 may then be removed byapplication of a developer solvent if a positive photosensitive polymeris used, or the unexposed portions may be removed if a negativephotosensitive polymer is used. Of course, in other embodiments, otherpatterning processes may be used. For example, a separate photoresistlayer may be deposited on top of the second dielectric layer 120 inorder to define and then transfer a desired pattern to the seconddielectric layer 120.

Additional chemical, physical or thermal processing may be carried outto cure or harden the second dielectric layer 120. For example, thepartially formed fan-out wafer level packaging 100 may be baked to curethe second dielectric layer 120.

Bumps 104 may then be formed at the redistributed bond pad, asillustrated in FIG. 11. The bumps 104 may comprise any of a variety ofconductive materials, as described above. In one embodiment, the bumps104 may comprise lead-free bumps, although in other embodiments leadedbumps may be used.

In one embodiment, the redistributed bond pad may simply be defined bythe portions of the redistribution layer 116 exposed through theredistribution vias 124, as illustrated in FIG. 11. In such anembodiment, the bumps 104 may be formed by conventional ball bondingtechniques in direct contact with the redistribution layer 116. Thus,the bumps 104 may be formed on the partially formed fan-out wafer levelpackaging 100 to form the completed fan-out wafer level packaging 100 ofFIG. 4.

In other embodiments, after forming the second dielectric layer 120, aredistributed bond pad may be formed at least partially within theredistribution via 124. Such a redistributed bond pad may comprise anunder-bump-metallurgy layer configured to facilitate the electricalconnection formed between the bump 104 and the redistribution layer 116.This redistributed bond pad may be formed by a variety of processes. Inone embodiment, the redistributed bond pad may be formed by sputtering acompound of either: (a) titanium, nickel and copper, or (b) aluminum,nickel and copper. The sputtered compound may then be plated with acompound of either: (a) titanium and copper, (b) titanium, tungsten andcopper, or (c) chromium and copper. In another embodiment, theredistributed bond pad may be formed by plating the exposedredistribution layer 116 with at least one of: (a) copper, (b) nickel,or (c) copper and nickel.

After the bump 104 is connected to the redistribution layer 116, thebottom surface, i.e., the backside of the IC 102 is thinned andplanarized. FIG. 12 illustrates planarization of the ICs 102. In oneembodiment, portions of the encapsulant layer 112 and the inactiveregion of the integrated circuit 102 that is exposed or covered by athin layer of encapsulant is ground away leaving 450 microns of the ICs.The vertical dotted lines illustrate where a die cutter or laser maysingulate the ICs 102.

FIG. 13 illustrates an alternative embodiment, where a backside coating130 protects the bottom surface 108 of the ICs 102 prior to singulation.The backside coating 130 may be an epoxy or other material suitable forprotecting the bottom surface 108 of the IC from damage. Additionally oralternatively, the backside coating may have a similar coefficient ofthermal expansion as the silicon of the IC 102. The layer 130 can bethin, so that if it has a CTE different from the die 102, there islittle to no additional stress put on the die 102 when it goes throughheating and cooling cycles. Another way to achieve this is to have thesame CTE for both materials, while yet another way is to have no layerover the back side 108. Usually, a prior art die would have height hbetween 800 and 2000 microns of resin above the bottom surface of thedie (see FIG. 1). In the standard packing of the prior art, a resinheight h of 1000 microns is common. When the package is repeatedlyheated and cooled, this huge bulk of resin, having a different CTE thanthe die 102, will put repeated stress on the die. On the other hand, oneembodiment of the present invention has no resin on the back side of thedie, avoiding the issue completely. In some embodiments, a thin layer ofmaterial under 120 microns and preferably in the range of about 40 to 90microns of material 130 is on the back side 108 of the die, with 80microns being preferred.

The material 130 can be a type of material having a CTE that is closerto that of the die than the encapsulating resin 112, thus providing evenless stress. It can also be an epoxy, a polymer, or other materialwhich, even though the CTE is different from the die, the height “h” isin the range of about 80 to 100 microns, thus not providing large stresson the die during heating and cooling cycles.

The completed fan-out wafer level packaging 100 is illustrated in FIG.4. After completing the processing acts described above upon a pluralityof contiguous packaging, the resulting wafer may be tested and thensingulated to form the individual fan-out wafer level packaging 100(e.g., via dicing or laser-cutting), as shown in FIGS. 12 and 13. Inother embodiments, the packaging 100 may have been singulated at anearlier stage in the process.

In one embodiment, the fan-out wafer level packaging 100 may be coupledto one or more additional chip packages or electronic devices via thebumps 104.

The foregoing detailed description has set forth various embodiments ofthe devices and/or processes via the use of block diagrams, schematics,and examples. Insofar as such block diagrams, schematics, and examplescontain one or more functions and/or operations, it will be understoodby those skilled in the art that each function and/or operation withinsuch block diagrams, flowcharts, or examples can be implemented,individually and/or collectively, by a wide range of hardware, software,firmware, or virtually any combination thereof. In one embodiment, thepresent subject matter may be implemented via Application SpecificIntegrated Circuits (ASICs). However, those skilled in the art willrecognize that the embodiments disclosed herein, in whole or in part,can be equivalently implemented in standard integrated circuits, as oneor more programs executed by one or more processors, as one or moreprograms executed by one or more controllers (e.g., microcontrollers),as firmware, or as virtually any combination thereof, and that designingthe circuitry and/or writing the code for the software and or firmwarewould be well within the skill of one of ordinary skill in the art inlight of this disclosure.

When logic is implemented as software and stored in memory, one skilledin the art will appreciate that logic or information can be stored onany computer readable storage medium for use by or in connection withany processor-related system or method. In the context of this document,a memory is a computer readable storage medium that is an electronic,magnetic, optical, or other physical device or means that contains orstores a computer and/or processor program and/or data or information.Logic and/or the information can be embodied in any computer readablestorage medium for use by or in connection with an instruction executionsystem, apparatus, or device, such as a computer-based system,processor-containing system, or other system that can fetch theinstructions from the instruction execution system, apparatus, or deviceand execute the instructions associated with logic and/or information.

The various embodiments described above can be combined to providefurther embodiments. From the foregoing it will be appreciated that,although specific embodiments have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the teachings. Accordingly, the claims are notlimited by the disclosed embodiments.

1. A method of manufacturing fan-out wafer level packaging, the methodcomprising: positioning an integrated circuit on a first surface;forming a layer of encapsulant on the first surface substantiallysurrounding the integrated circuit, the layer of encapsulant having aheight substantially equal to a height of the integrated circuit;forming a redistribution layer configured to electrically couple a bondpad of the integrated circuit to a redistributed bond pad; and forming abump at the redistributed bond pad.
 2. The method of claim 1, whereinpositioning the integrated circuit on the first surface includespositioning the integrated circuit on an adhesive surface of a piece oftape.
 3. The method of claim 2, wherein the height of the layer ofencapsulant is equal to the height of the integrated circuit.
 4. Themethod of claim 3, further comprising curing the encapsulant, andremoving the piece of tape.
 5. The method of claim 4, wherein, uponremoving the piece of tape, a top surface and a bottom surface of theintegrated circuit are both exposed, and the layer of encapsulantsubstantially covers four side surfaces of the integrated circuit. 6.The method of claim 2, wherein the integrated circuit is positioned onthe adhesive surface with the bond pad of the integrated circuit facingthe adhesive surface.
 7. The method of claim 1, wherein the height ofthe layer of encapsulant is less than 10% greater than the height of theintegrated circuit.
 8. The method of claim 1, further comprising forminga first dielectric layer extending at least partially over a top surfaceof the integrated circuit, the first dielectric layer including a bondpad via through which at least a portion of the bond pad is exposed. 9.The method of claim 9, wherein forming the redistribution layer includesforming the redistribution layer over at least a portion of the firstdielectric layer, and filling at least partially the bond pad via with aportion of the redistribution layer.
 10. The method of claim 9, whereinforming the redistribution layer includes: sputtering a seed layer overthe first dielectric layer and within the bond pad via; forming apatterned layer over the seed layer using photolithography; plating atleast a portion of the seed layer exposed through the patterned layer toform the redistribution layer; removing the patterned layer; andremoving at least a remaining portion of the seed layer that is notplated.
 11. The method of claim 11, wherein the redistribution layerincludes the redistributed bond pad, and wherein forming the bumpincludes forming the bump in direct contact with the redistributionlayer.
 12. The method of claim 9, further comprising forming a seconddielectric layer extending at least partially over the redistributionlayer, the second dielectric layer including a redistribution viathrough which at least a portion of the redistribution layer is exposed.13. The method of claim 8, further comprising, after forming the seconddielectric layer, forming the redistributed bond pad at least partiallywithin the redistribution via.
 14. A method of manufacturing fan-outwafer level packaging, the method comprising: positioning an activesurface of an integrated circuit on a first surface; placing an inactivesurface of the integrated circuit in an encapsulant in a moldingchamber; and compressing the first surface towards the encapsulant inthe molding chamber to cover all sides of the integrated circuit withencapsulant and to prevent the encapsulant from covering the inactivesurface and the active surface of the integrated circuit.
 15. The methodof claim 14, further comprising compressing the first surface until theinactive surface of the integrated circuit is adjacent a bottom interiorsurface of the molding chamber.
 16. The method of claim 15, furthercomprising protecting the integrated circuit by forming a protectivelayer adjacent the bottom interior surface of the molding chamber. 17.The method of claim 14, further comprising removing the integratedcircuit from the molding chamber and removing the first surface from theintegrated circuit.
 18. The method of claim 17 wherein a height of theencapsulant is substantially equal to a height of the integratedcircuit.
 19. The method of claim 17, further comprising forming aredistribution layer configured to electrically couple a bond pad of theintegrated circuit to a redistributed bond pad.
 20. The method of claim19, further comprising forming a bump on the redistributed bond pad. 21.A method of forming an encapsulation layer for fan-out wafer levelpackaging, comprising: positioning a first surface of an integratedcircuit on a carrier; and compressing the integrated circuit into amolding chamber having an encapsulant therein, the molding chamber sizedand shaped to allow a second surface of the integrated circuit tocontact a bottom surface of the molding chamber.
 22. The method of claim21 wherein the integrated circuit is compressed into the molding chamberby applying a force to a surface of the carrier not in contact with theintegrated circuit.
 23. The method of claim 21 wherein the bottomsurface of the molding chamber is covered with a protective layer toprevent damage to the integrated circuit.
 24. The method of claim 21wherein the carrier includes an adhesive layer and a support layer, theintegrated circuit separated from the support layer by the adhesivelayer.